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Welcome to Thanyapat Sakunkonchak homepage

Ph.D., University of Tokyo, 2004.

I'm the Postdoctoral Researcher at Fujita Laboratory, VLSI Design and Education Center (English), University of Tokyo.
You can contact me via the address below.

Short Biography

Born		August 29, 1976
Birth place		Bangkok, Thailand
Nationality		Thai
Religious		Buddhism

Office

Fujita Laboratory, Takeda Building 407
VLSI Design and Education Center (VDEC)
University of Tokyo
2-11-16 Yayoi, Bunkyo-ku, Tokyo 113-0032 JAPAN
Phone & Fax: +81-3-5841-6764
Email: thong \at cad . t . u - tokyo . ac . jp , thanyapat \at gmail . com
Homepage: http://www.cad.t.u-tokyo.ac.jp/~thong

Research Interests

Formal Verification. Hardware/Software Verification. Model Checking Techniques. Program Analysis. Synchronization Verification. System-Level Verification. Equivalence Checking.

Software

A tool for synchronization verification (S-VeT)